1. Field of the Invention
The present invention relates generally to a television receiver and, more particularly, is directed to an automatic level adjusting system suitable for use as an automatic white balance adjusting circuit of a television receiver.
2. Description of the Prior Art
A prior-art television receiver is provided with an automatic white balance adjusting circuit in order to obtain white color of the same chromaticity regardless of the change of the brightness level.
FIG. 1 (FIG. 1 is formed of FIGS. 1A and 1B with FIG. 1A to the left of and partly overlapping FIG. 1B) is a block diagram showing a television receiver having an automatic white balance adjusting circuit that is previously proposed by the same assignee of the present application. This television receiver is disclosed in official gazette of Japanese laid-open patent application No. 60-186185 and will be described herein-below.
Referring to FIG. 1, a television broadcast signal is received at an antenna 1 and is supplied through a tuner 2, a video intermediate frequency (VIF) amplifying circuit 3 to a video detecting circuit 4 which produces a video signal S.sub.V and supplies the same to a Y/C separating circuit 5. The Y/C separating circuit 5 separates the video signal S.sub.V into a luminance signal Y and a chroma signal C which are then fed to a video processing circuit 6 and to a chroma signal reproducing circuit 7, respectively. The video processing circuit 6 processes the luminance signal Y such that it undergoes picture-adjustment, level-clamping or the like. The, thus processed, luminance signal Y is supplied to an RGB matrix circuit 8. The chroma signal reproducing circuit 7 effects color-demodulation by utilizing a color burst signal, thereby producing color difference signals R-Y and B-Y. The color difference signals R-Y and B-Y are then supplied to the RGB matrix circuit 8.
Further, the video signal S.sub.V from the video detecting circuit 4 is supplied to a synchronizing separating circuit 9, from which horizontal and vertical synchronizing signals H.sub.SYNC and V.sub.SYNC are derived. The horizontal and vertical synchronizing signals H.sub.SYNC and V.sub.SYNC are supplied to a horizontal deflection circuit 10 and a vertical deflection circuit 11, respectively. The horizontal deflection circuit 10 generates a horizontal blanking pulse HP in synchronism with the horizontal synchronizing signal H.sub.SYNC and supplies it to the RGB matrix circuit 8 and to a timing pulse generating circuit 22 that will be described later. Also, a horizontal deflection signal HF is generated from the horizontal deflection circuit 10 and is fed to a horizontal deflection coil (not shown). Similarly, the vertical deflection circuit 11 generates a vertical blanking pulse VP in synchronism with the vertical synchronizing signal V.sub.SYNC and supplies to the RGB matrix circuit 8 and to the timing pulse generating circuit 22. A vertical deflection signal VF is generated from the vertical deflection circuit 11 and is fed to a vertical deflection coil (not shown).
The RGB matrix circuit 8 generates three primary color signals, for example, a red signal R, a green signal G and a blue signal B on the basis of the luminance signal Y, the color difference signals R-Y and B-Y and the horizontal and vertical blanking pulses HP and VP. The RGB matrix circuit 8 supplies the red, green and blue primary color signals R, G and B to an R-component output circuit 12R, a G-component output circuit 12G and a B-component output circuit 12B. The output circuits 12R, 12G and 12B are each constructed in the same way and therefore only the B-component output circuit 12B will be described in detail, for simplicity.
The B-component output circuit 12B comprises a reference level inserting circuit 13, a gain control amplifying circuit 14 and a level shifting circuit 15. The reference level inserting circuit 13 is operative to add the blue signal B with a white reference level V.sub.SW or a black reference level V.sub.SB that will be described later. The gain control amplifying circuit 14 is operative to adjust the white level of the blue signal B in response to a control signal S.sub.WB which will be described later. The level shifting circuit 15 is operative to adjust the black level of the blue signal B in response to a control signal S.sub.BB which will be described later.
The B-component output circuit 12B further includes differential amplifiers 16, 17 and sample-and-hold (S/H) circuits 18, 19. Both of the sample-and-hold circuits 18 and 19 sample and hold a voltage corresponding to a current flowing through a blue cathode 21B of a cathode ray tube (CRT) 20 at predetermined timings and supply the thus held outputs to non-inverting input terminals of the differential amplifiers 16 and 17. The differential amplifiers 16 and 17 receive at their inverting input terminals a reference level signal V.sub.O, and feed the control signals S.sub.BB and S.sub.WB, which correspond to a difference between the signals fed from the sample-and-hold circuits 18, 19 and the reference level signal V.sub.O, back to the level shifting circuit 15 and the gain control amplifying circuit 14, respectively.
The blue signal B from the B-component output circuit 12B is supplied to transistors Q3 and Q6 and is thereby converted to a cathode current that flows to the blue cathode 21B of the cathode ray tube 20. In a like manner, transistors Q1 and Q4 are provided in association with a red cathode 21R of the cathode ray tube 20, while transistors Q2 and Q5 are provided in association with a green cathode 21G of the cathode ray tube 20, respectively. The transistors Q4, Q5 and Q6 are respectively connected with resistors R4, R5 and R6 having resistance values M.sub.1, M.sub.2 and M.sub.3 in order to detect cathode currents for the black level. Also, resistors R1, R2 and R3, having corresponding resistance values r.sub.1, r.sub.2 and r.sub.3, are provided in order to detect cathode currents for the white level. The resistance values M.sub.i and r.sub.i have established therebetween a relationship that is expressed as EQU M.sub.i :r.sub.i .apprxeq.100:1
The collectors of the transistors Q4, Q5 and Q6 are connected together to a single junction J via diodes D4, D5 and D6, and a cathode current signal E developed at the junction J is commonly supplied to the sample-and-hold circuits 18 and 19 in the R, G and B-component output circuits 12R, 12G and 12B. The resistors R1, R2 and R3 having small resistance value r.sub.i are connected in common through diodes D1, D2 and D3, respectively, to one fixed contact of a switch 25 whose other fixed contact is grounded.
A timing pulse generating circuit 22 will now be described in detail with reference to FIGS. 1A and 1B and waveform diagrams forming FIGS. 2A to 2E.
The timing pulse generating circuit 22 successively generates white level adjusting pulse signals P.sub.WR, P.sub.WG and P.sub.WB during a 16th horizontal period (16H) to an 18th horizontal period (18H) as shown in FIGS. 2B-2E. The waveforms of the pulse signals P.sub.WR, P.sub.WG and P.sub.WB are illustrated in FIGS. 2C, 2D and 2E, respectively. The timing pulse generating circuit 22 also generates sampling pulse signals P.sub.WR1, P.sub.WG1 and P.sub.WB1 (FIG. 1) in synchronism with the series of pulse signals P.sub.WR, P.sub.WG and P.sub.WB. During this period, the timing pulse generating circuit 22 closes the switch 25 by delivering to it a control signal P1. During the next field, the timing pulse generating circuit 22 opens the switch 25 by the control signal P1 to generate black level adjusting pulse signals P.sub.BR, P.sub.BG and P.sub.BB in series. In synchronism therewith, the timing pulse generating circuit 22 generates sampling pulse signals P.sub.BR1, P.sub.BG1 and P.sub.BB1 in series. The white level adjusting pulse signals P.sub.WR, P.sub.WG and P.sub.WB are converted to white reference level signals V.sub.SW by a white reference level setting circuit 23 and are fed to the corresponding reference level inserting circuits 13, respectively. On the other hand, the black level adjusting pulse signals P.sub.BR, P.sub.BG and P.sub.BB are, respectively, converted to black reference level signals V.sub.SB by a black reference level setting circuit 24 and are fed to the corresponding reference level inserting circuits 13.
In this prior-art example, assuming that the black level is 5 IRE and that the white level is 50 IRE, then the resistance values r.sub.3, M.sub.3 and the comparing voltage V.sub.O will be determined so as to satisfy the equation expressed as EQU I.sub.W r.sub.3 .apprxeq.I.sub.B M.sub.3 .apprxeq.V.sub.O
where I.sub.B and I.sub.W are the cathode currents of black and white levels flowing to the blue cathode 21B of the cathode ray tube 20, respectively. If the resistance values r.sub.3, M.sub.3 and the comparing voltage V.sub.O are determined as described above, when the white level is pre-determined, the control signal S.sub.WB proportional to error is generated from the differential amplifier 17 and is fed to the gain control amplifying circuit 14, thereby correcting the gain of the gain control amplifying circuit 14. Also, when the black level is pre-determined, the control signal S.sub.BB proportional to error is generated from the differential amplifier 16 and is fed to the level shifting circuit 15, thereby correcting its cut-off level.
Particularly, in this prior-art example, the black level adjustment and the white level adjustment are effected alternately at every field. In addition, the level adjustment of R, G and B signals are sequentially carried out at every horizontal period H within the same field.
The prior-art white level adjustment is set out as above, and in other words, it will be summarized as follows.
In practice, a reference pulse signal (i.e. corresponding to a horizontal scanning line having an amount of light corresponding to the black or white level) is produced on the cathode ray tube and a voltage-converted-value of the cathode current at that time is compared with a previously-corrected reference voltage, whereby the drive current for a cathode is adjusted so as to remove error, thus the white level being adjusted. The horizontal scanning line having an amount of light corresponding to the black or white level is inserted into a so-called over-scan area or an under-scan area of the cathode ray tube so that it is not seen by the viewer.
FIG. 3 is a front view pictorially illustrating the viewing screen 27 of a television receiver 26. As shown in FIG. 3, the television receiver 26 has a viewable picture screen portion 27, which is bordered in full line in the figure. The fluorescent screen of the cathode ray tube 20 is constructed larger than the viewable portion of the television picture screen 27, in practice. Now, let it be assumed that in the odd field the vertical blanking begins with the 1st horizontal period 1H and ends with the 14th horizontal period 14H. In other words, a so-called retrace period of the horizontal scanning line lies between horizontal scanning lines 1H and 14H. The horizontal scanning lines from 15H to 18H reside in an over-scan area 28 that is outside the viewable portion of the television picture screen 27 while some scanning lines reside in an under-scan area 29.
While the white or black level reference pulse signal can be inserted into only the over-scan area 28 or the under-scan area 29, in the example of FIG. 1, the white level reference pulse signals of R, G and B channels are inserted into the scanning lines 16H to 18H as shown in FIG. 2, in which case no trouble occurs.
Recently, there have been developed various kinds of cathode ray tubes, and particularly, cathode ray tubes having a large television picture screen are given a long retrace period. FIG. 4 shows a television receiver 26A having a cathode ray tube 20A of which the retrace period ranges from 1H to 17H. In this case, the over-scan area 28, which is not within the viewable portion of the television picture screen 27A, includes only the horizontal scanning lines from 18H to 20H. The retrace period of the horizontal scanning line becomes different depending on the types of the television receiver because the characteristic of the deflection yoke used therein is changed with, mainly, the size of the cathode ray tube. Further, some known television monitor receivers for computers have an over-scan area that is smaller than the standard one.
In the prior-art automatic white balance adjusting circuit used in the television receiver shown in FIG. 1, however, in order to change the insertion position of the white or black level reference pulse signal (with which horizontal scanning period the insertion of the white or black level reference pulse signal begins), the timing pulse generating circuit 22 has to be exchanged or resistors and the like have to be exchanged. Eventually, in the prior-art television receiver, the standardization of its hardware does not make a remarkable progress.